The present inventive concepts relate to a memory system including a controller and a semiconductor memory device. More particularly, the present inventive concepts relate to a memory controller having a memory bad page management function and a bad page management method thereof.
In a semiconductor memory device, if even one of a plurality of memory cells has a flaw, the semiconductor memory device cannot perform a desired function and is treated as a defective product. However, when only a small number of memory cells have flaws, it is inefficient to treat the semiconductor memory device as a defective product, the yield is decreased.
In order to prevent this problem, a semiconductor memory device may include a spare memory cell block having spare memory cells. When defects occur in normal memory cells of a normal memory cell block, failed memory cells are replaced with spare memory cells in the spare memory cell block and, thereby, the semiconductor memory device is not treated as a defective product.
Failed memory cells of the semiconductor memory device may be replaced with spare memory cells from the spare memory cell block by a row/column unit. An anti-fuse usually may be used as a program device which stores fail addresses to perform replacement work. For example, if failed memory cells are found in the semiconductor memory device during a wafer test, after a wafer process is completed, a fail address indicating an address of a failed memory cell is programmed by rupturing anti-fuses. Thus, when a row/column address accessing a failed memory cell is input, a row/column of a spare memory cell in the spare memory cell block is activated instead of the failed memory cell by using information programmed in the anti-fuses or an e-fuse.
A page of a memory cell array in a memory such as a DRAM may mean a word line. Thus, a page address means a row address for accessing a word line. If a page address is applied to a DRAM and, thereby, a word line is activated, memory cells connected to the page address are all accessed. An access operation includes an operation of enabling a word line connected to memory cells for a read or write operation of a memory cell.
If a failed memory cell is found in a DRAM during testing, a word line connected to the failed memory cell is managed as a bad page. Bad page management includes a redundancy scheme in which, after a bad page address is programmed using an anti-fuse or an e-fuse and the programmed bad page address is stored in an internal latch circuit, when a DRAM is powered up, a spare page is accessed instead of the bad page when an external input address indicating an address of the bad page is applied to the DRAM.
Including a latch circuit and a functional circuit for performing a redundancy scheme, as described above, in a DRAM causes an overhead of a chip size of the DRAM.
In a nonvolatile semiconductor memory device such as a flash memory, a controller may perform a function of managing a bad page. However, since latency of a data input/output operation of a DRAM is very performance-critical, it is inappropriate to apply technologies adopted by a controller of a nonvolatile semiconductor memory device to a volatile memory device.